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Jlm
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This is the complete list of members for jlm::hls::RhlsToFirrtlConverter, including all inherited members.
| AddAddOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddAndOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddAsSIntOp(mlir::Block *body, mlir::Value value) | jlm::hls::RhlsToFirrtlConverter | private |
| AddAsUIntOp(mlir::Block *body, mlir::Value value) | jlm::hls::RhlsToFirrtlConverter | private |
| AddBitsOp(mlir::Block *body, mlir::Value value, int high, int low) | jlm::hls::RhlsToFirrtlConverter | private |
| AddBundlePort(::llvm::SmallVector< circt::firrtl::PortInfo > *ports, circt::firrtl::Direction direction, std::string name, circt::firrtl::FIRRTLBaseType type) | jlm::hls::RhlsToFirrtlConverter | private |
| AddClockPort(::llvm::SmallVector< circt::firrtl::PortInfo > *ports) | jlm::hls::RhlsToFirrtlConverter | private |
| AddCvtOp(mlir::Block *body, mlir::Value value) | jlm::hls::RhlsToFirrtlConverter | private |
| AddDivOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddDShlOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddDShrOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddEqOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddGeqOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddGtOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddInstanceOp(mlir::Block *circuitBody, jlm::rvsdg::Node *node) | jlm::hls::RhlsToFirrtlConverter | private |
| AddLeqOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddLtOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddMemReqPort(::llvm::SmallVector< circt::firrtl::PortInfo > *ports) | jlm::hls::RhlsToFirrtlConverter | private |
| AddMemResPort(::llvm::SmallVector< circt::firrtl::PortInfo > *ports) | jlm::hls::RhlsToFirrtlConverter | private |
| AddMulOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddMuxOp(mlir::Block *body, mlir::Value select, mlir::Value high, mlir::Value low) | jlm::hls::RhlsToFirrtlConverter | private |
| AddNeqOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddNodeOp(mlir::Block *body, mlir::Value value, std::string name) | jlm::hls::RhlsToFirrtlConverter | private |
| AddNotOp(mlir::Block *body, mlir::Value first) | jlm::hls::RhlsToFirrtlConverter | private |
| AddOrOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddPadOp(mlir::Block *body, mlir::Value value, int amount) | jlm::hls::RhlsToFirrtlConverter | private |
| AddRemOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddResetPort(::llvm::SmallVector< circt::firrtl::PortInfo > *ports) | jlm::hls::RhlsToFirrtlConverter | private |
| AddSubOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| AddWhenOp(mlir::Block *body, mlir::Value condition, bool elseStatment) | jlm::hls::RhlsToFirrtlConverter | private |
| AddWireOp(mlir::Block *body, std::string name, int size) | jlm::hls::RhlsToFirrtlConverter | private |
| AddXorOp(mlir::Block *body, mlir::Value first, mlir::Value second) | jlm::hls::RhlsToFirrtlConverter | private |
| Builder_ | jlm::hls::RhlsToFirrtlConverter | private |
| check_module(circt::firrtl::FModuleOp &module) | jlm::hls::RhlsToFirrtlConverter | private |
| Connect(mlir::Block *body, mlir::Value sink, mlir::Value source) | jlm::hls::RhlsToFirrtlConverter | private |
| ConnectInvalid(mlir::Block *body, mlir::Value value) | jlm::hls::RhlsToFirrtlConverter | private |
| Context_ | jlm::hls::RhlsToFirrtlConverter | private |
| ConvertToMduleOp(llvm::LlvmRvsdgModule &rvsdgModule) | jlm::hls::RhlsToFirrtlConverter | inline |
| create_node_names(rvsdg::Region *r) | jlm::hls::BaseHLS | protected |
| DefaultFIRVersion_ | jlm::hls::RhlsToFirrtlConverter | private |
| DropMSBs(mlir::Block *body, mlir::Value value, int amount) | jlm::hls::RhlsToFirrtlConverter | private |
| extension() override | jlm::hls::RhlsToFirrtlConverter | inlineprivatevirtual |
| get_base_file_name(const llvm::LlvmRvsdgModule &rm) | jlm::hls::BaseHLS | protectedstatic |
| get_hls_lambda(llvm::LlvmRvsdgModule &rm) | jlm::hls::BaseHLS | protected |
| get_mem_reqs(const rvsdg::LambdaNode &lambda) | jlm::hls::BaseHLS | inlineprotected |
| get_mem_resps(const rvsdg::LambdaNode &lambda) | jlm::hls::BaseHLS | inlineprotected |
| get_node_name(const rvsdg::Node *node) | jlm::hls::BaseHLS | protected |
| get_port_name(jlm::rvsdg::Input *port) | jlm::hls::BaseHLS | protectedstatic |
| get_port_name(jlm::rvsdg::Output *port) | jlm::hls::BaseHLS | protectedstatic |
| get_reg_args(const rvsdg::LambdaNode &lambda) | jlm::hls::BaseHLS | inlineprotected |
| get_reg_results(const rvsdg::LambdaNode &lambda) | jlm::hls::BaseHLS | inlineprotected |
| GetBundleType(const circt::firrtl::FIRRTLBaseType &type) | jlm::hls::RhlsToFirrtlConverter | private |
| GetClockSignal(circt::firrtl::FModuleOp module) | jlm::hls::RhlsToFirrtlConverter | private |
| GetConstant(mlir::Block *body, int size, int value) | jlm::hls::RhlsToFirrtlConverter | private |
| GetFirrtlType(const jlm::rvsdg::Type *type) | jlm::hls::RhlsToFirrtlConverter | private |
| GetInPort(circt::firrtl::FModuleOp &module, size_t portNr) | jlm::hls::RhlsToFirrtlConverter | private |
| GetInstancePort(circt::firrtl::InstanceOp &instance, std::string portName) | jlm::hls::RhlsToFirrtlConverter | private |
| GetIntType(int size) | jlm::hls::RhlsToFirrtlConverter | private |
| GetIntType(const jlm::rvsdg::Type *type, int extend=0) | jlm::hls::RhlsToFirrtlConverter | private |
| GetInvalid(mlir::Block *body, int size) | jlm::hls::RhlsToFirrtlConverter | private |
| GetModuleName(const rvsdg::Node *node) | jlm::hls::RhlsToFirrtlConverter | private |
| GetOutPort(circt::firrtl::FModuleOp &module, size_t portNr) | jlm::hls::RhlsToFirrtlConverter | private |
| GetPort(circt::firrtl::FModuleOp &module, std::string portName) | jlm::hls::RhlsToFirrtlConverter | private |
| GetReadyElement() | jlm::hls::RhlsToFirrtlConverter | private |
| GetResetSignal(circt::firrtl::FModuleOp module) | jlm::hls::RhlsToFirrtlConverter | private |
| GetSubfield(mlir::Block *body, mlir::Value value, int index) | jlm::hls::RhlsToFirrtlConverter | private |
| GetSubfield(mlir::Block *body, mlir::Value value, ::llvm::StringRef fieldName) | jlm::hls::RhlsToFirrtlConverter | private |
| GetText(llvm::LlvmRvsdgModule &) override | jlm::hls::RhlsToFirrtlConverter | inlinevirtual |
| GetValidElement() | jlm::hls::RhlsToFirrtlConverter | private |
| InitializeMemReq(circt::firrtl::FModuleOp module) | jlm::hls::RhlsToFirrtlConverter | private |
| IsIdentityMapping(const rvsdg::MatchOperation &op) | jlm::hls::RhlsToFirrtlConverter | private |
| JlmSize(const jlm::rvsdg::Type *type) | jlm::hls::BaseHLS | static |
| MlirGen(const rvsdg::LambdaNode *lamdaNode) | jlm::hls::RhlsToFirrtlConverter | |
| MlirGen(LoopNode *loopNode, mlir::Block *circuitBody) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGen(rvsdg::Region *subRegion, mlir::Block *circuitBody) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGen(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenAddrQueue(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenBranch(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenBuffer(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenDMux(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenExtModule(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenFork(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenHlsDLoad(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenHlsLoad(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenHlsLocalMem(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenHlsMemReq(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenHlsMemResp(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenHlsStore(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenLoopConstBuffer(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenMem(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenNDMux(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenPredicationBuffer(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenPrint(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenSimpleNode(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenSink(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenStateGate(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| MlirGenTrigger(const jlm::rvsdg::SimpleNode *node) | jlm::hls::RhlsToFirrtlConverter | private |
| modules | jlm::hls::RhlsToFirrtlConverter | private |
| node_map | jlm::hls::BaseHLS | protected |
| nodeToModule(const jlm::rvsdg::Node *node, bool mem=false) | jlm::hls::RhlsToFirrtlConverter | private |
| operator=(const RhlsToFirrtlConverter &)=delete | jlm::hls::RhlsToFirrtlConverter | |
| operator=(RhlsToFirrtlConverter &&)=delete | jlm::hls::RhlsToFirrtlConverter | |
| output_map | jlm::hls::BaseHLS | protected |
| RhlsToFirrtlConverter() | jlm::hls::RhlsToFirrtlConverter | inline |
| RhlsToFirrtlConverter(const RhlsToFirrtlConverter &)=delete | jlm::hls::RhlsToFirrtlConverter | |
| RhlsToFirrtlConverter(RhlsToFirrtlConverter &&)=delete | jlm::hls::RhlsToFirrtlConverter | |
| run(llvm::LlvmRvsdgModule &rm) | jlm::hls::BaseHLS | inline |
| ToString(llvm::LlvmRvsdgModule &rvsdgModule) | jlm::hls::RhlsToFirrtlConverter | inline |
| toString(const circt::firrtl::CircuitOp circuit) | jlm::hls::RhlsToFirrtlConverter | private |
| TraceArgument(rvsdg::RegionArgument *arg) | jlm::hls::RhlsToFirrtlConverter | private |
| TraceStructuralOutput(rvsdg::StructuralOutput *out) | jlm::hls::RhlsToFirrtlConverter | private |
| WriteCircuitToFile(const circt::firrtl::CircuitOp circuit, std::string name) | jlm::hls::RhlsToFirrtlConverter | |
| WriteModuleToFile(const circt::firrtl::FModuleOp fModuleOp, const rvsdg::Node *node) | jlm::hls::RhlsToFirrtlConverter | |
| ~BaseHLS() | jlm::hls::BaseHLS | virtual |
1.9.1